1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to an EDRAM, in which a DRAM is co-resident with a high-speed CMOS logic circuit.
2. Description of the Related Art
In LSI production, commodity DRAMs placing importance on mass-productivity and cost and logic LSIs placing importance on a high speed and a high function are considered as two pillars, and they have been produced respectively. Due to the advancement of a miniaturization technique and the like, an EDRAM having the faculties of both the DRAM and the logic LSI are put into practical use. In the EDRAM, a band width connecting a DRAM to a logic circuit can be widened, which enables high-speed data processing to be performed. Thus, the EDRAM is considered as a key device in an information society that requires high-speed processing of a large amount of data.
In order for a commodity DRAM to be co-resident with a high-speed logic, a number of novel techniques and improvement of a fabrication process, such as shortened heat treatment time for forming a capacitive film, are required. It also is necessary to improve the layout of a sense amplifier of a DRAM. This problem will be described below with reference to the drawings.
FIG. 5 is a plan view showing a mask layout of a conventional CMOS sense amplifier transistor of a DRAM.
In FIG. 5, a region I is a N-type sense amplifier transistor pair region formed on a P-type semiconductor substrate, and a region II is a P-type sense amplifier transistor pair region formed on a N-type semiconductor substrate. The sense amplifier transistor has a ring-type gate electrode 504. Drain regions of a pair of upper and lower transistors in the ring-type gate electrodes 504 are connected in a diagonally crossed manner to bit lines 507 made of upper layer metal wiring to form a differential circuit. Furthermore, reference numeral 509 denotes a power source line connected to a source region between a pair of ring-type gate electrodes 504.
In the above-mentioned sense amplifier, three sides of the ring-type gate electrode are used as channels. Therefore, a large gate width can be realized in a small area, and a transistor with high ability can be used. Furthermore, a drain region is limited to a small region surrounded by the ring-type gate electrode 504, so that diffusion capacitance is small and a high-speed operation is made possible.
However, in a layout of a conventional sense amplifier, a parasitic capacitor (gate overlap capacitor) is formed in a portion where one side of the ring-type gate electrode 504 that does not function as a transistor is overlapped with an active region 503, which degrades a high-speed property. In particular, in an advanced miniaturization process (e.g., 0.18 xcexcm rule), a gate oxide film is made thin to about 35 nm, and the gate overlap capacitance thereof is very large, which is a serious problem.
Furthermore, due to a mask alignment shift during formation of an active region and during formation of a gate electrode, the gate overlap capacitance of a pair of upper and lower transistors is changed. Therefore, the ability balance between a pair of transistors is degraded, resulting in a decrease in sensitivity of the sense amplifier.
Furthermore, the ring-type gate electrode has a small depth of focus (DOF) at a corner portion thereof during lithography and a gate length varies greatly. As a result, a difference in characteristics is caused between a pair of transistors. This problem becomes more serious due to the advancement of miniaturization.
Furthermore, in a region in the ring-type gate electrode, during the salicide process for reducing parasitic resistance, the deposited film thickness of metal with a high melting point is made small due to insufficient coverage. As a result, a junction leakage is increased by the defective formation of silicide, causing a problem in a sense operation. Furthermore, there is a problem such as an increase in a stand-by current of a circuit.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor device in which the difference in characteristics between a pair of sense amplifier transistors of a DRAM is suppressed, whereby the sensitivity of a sense amplifier is enhanced.
In order to achieve the above-mentioned object, a first semiconductor device of the present invention includes a DRAM region and a high-speed CMOS logic region that are co-resident with each other. A pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM are disposed respectively in one active region in parallel to each other in the same direction as that of bit lines, and a pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors are isolated by shallow trench isolation (STI) regions.
According to the above configuration, by placing the gate electrodes of the sense amplifier transistors in a line-and-space shape, the difference in transistor characteristics is suppressed, whereby a sense amplifier with high performance can be formed.
Furthermore, in the first semiconductor device of the present invention, it is preferable that floating electrodes are disposed on the shallow trench isolation regions between the pair of adjacent N-type sense amplifier transistors and between the pair of adjacent P-type sense amplifier transistors so as to be parallel to the pair of gate electrodes of each of the sense amplifier transistors. In this case, it is preferable that the pair of gate electrodes and the floating electrodes are disposed at a substantially equal interval.
According to the above configuration, by placing the gate electrodes of the sense amplifier transistors and the floating electrodes in a line-and-space shape at a substantially equal interval, the difference in transistor characteristics is suppressed, whereby a sense amplifier with high performance can be formed.
In order to achieve the above-mentioned object, a second semiconductor device of the present invention includes a DRAM region and a high-speed CMOS logic region that are co-resident with each other, wherein a pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM are disposed respectively in one active region in parallel to each other in the same direction as that of bit lines, active regions are connected to each other in a pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors, and on the active regions, field shield electrodes are disposed between the pair of adjacent N-type sense amplifier transistors and between the pair of adjacent P-type sense amplifier transistors so as to be parallel to the pair of gate electrodes of each of the sense amplifier transistors.
In the second semiconductor device of the present invention, it is preferable that the pair of gate electrodes and the field shield electrodes are disposed at a substantially equal interval.
According to the above configuration, by placing the gate electrodes of the sense amplifier transistors and the field shield electrodes in a line-and-space shape at a substantially equal interval, the difference in transistor characteristics is suppressed, and by using field shield isolation, the area of the transistor active region can be enlarged, and the influence of process stress is suppressed, whereby a sense amplifier with high performance can be formed.
In order to achieve the above-mentioned object, a third semiconductor device of the present invention includes a DRAM region and a high-speed CMOS logic region that are co-resident with each other. A pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM are disposed respectively in one active region in parallel to each other in the same direction as that of bit lines. Active regions are connected to each other in a pair of adjacent N-type sense amplifier transistors. On the active regions, a field shield electrode is disposed between the pair of adjacent N-type sense amplifier transistors so as to be parallel to the pair of gate electrodes of the N-type sense amplifier transistor, a pair of adjacent P-type sense amplifier transistors are isolated by shallow trench isolation (STI) regions, and a floating electrode is disposed on the shallow trench isolation region between the pair of P-type sense amplifier transistors so as to be parallel to the pair of gate electrodes of the P-type sense amplifier transistor.
In the third semiconductor device of the present invention, it is preferable that the pair of gate electrodes of the N-type sense amplifier transistor and the field shield electrodes, and the pair of gate electrodes of the P-type sense amplifier transistor and the floating electrodes are disposed at a substantially equal interval.
According to the above configuration, by placing the gate electrodes of the N-type sense amplifier transistors and the field shield electrodes in a line-and-space shape at a substantially equal interval, and by placing the gate electrodes of the P-type sense amplifier transistors and the floating electrodes in a line-and-space shape at a substantially equal interval, the difference in transistor characteristics is suppressed. By using field shield isolation in the N-type sense amplifier transistor region, and by using STI isolation in the P-type sense amplifier transistor region, an influence of process stress is suppressed. Thus, a sense amplifier having high performance and excellent in current cut characteristics, can be formed.
Furthermore, in the second or third semiconductor device of the present invention, it is preferable that a negative voltage used for a ground potential or a substrate potential of a DRAM cell is applied to the field shield electrodes on the N-type active regions.